Download Advanced ASIC chip synthesis: using Synopsys Design by Himanshu Bhatnagar PDF

By Himanshu Bhatnagar

Complex ASIC Chip Synthesis: utilizing Synopsys TM layout CompilerTM actual CompilerTM and PrimeTime TM, moment version describes the complicated recommendations and methods used in the direction of ASIC chip synthesis, actual synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. furthermore, the complete ASIC layout circulation technique special for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.

The emphasis of this publication is on real-time software of Synopsys instruments, used to wrestle quite a few difficulties visible at VDSM geometries. Readers may be uncovered to a good layout technique for dealing with complicated, sub-micron ASIC designs. importance is put on HDL coding types, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to format, actual synthesis, and static timing research. At each one step, difficulties with regards to each one section of the layout move are pointed out, with suggestions and work-around defined intimately. moreover, the most important matters concerning structure, such as clock tree synthesis and back-end integration (links to structure) also are mentioned at size. moreover, the booklet comprises in-depth discussions at the foundation of Synopsys expertise libraries and HDL coding kinds, precise in the direction of optimum synthesis resolution. goal audiences for this booklet are training ASIC layout engineers and masters point scholars project complex VLSI classes on ASIC chip layout and DFT recommendations.

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Additional resources for Advanced ASIC chip synthesis: using Synopsys Design Compiler, Physical Compiler, and PrimeTime

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In addition, if a hierarchical place and route has been performed, the physical placement location of cells in the PDEF format should also be generated. 1 Post-Layout Static Timing Analysis using PrimeTime The first step after layout is to perform static timing on the design, using the actual delays. Similar to post-placement, the post-route timing analysis uses the same commands, except that this time the actual delays are back annotated to the design. Predominantly, the timing of the design is dependent upon clock latency and skew.

The static timing was performed using PT; therefore it is prudent that the SDF file be generated from PT itself as shown in the previous scripts. However, some designers feel comfortable in using DC to generate the SDF file. We will therefore use DC to generate the SDF in this section. In addition, depending on the design, the resultant SDF file may require a certain amount of “massaging” before it can be used to perform timing simulation of the design. The reason for massaging is explained in detail in Chapter 11.

10. Extract real timing delays from the detailed routed design. 11. Back-annotate the real extracted data to PrimeTime. 12. Post-layout static timing analysis using PrimeTime. 13. Functional gate-level simulation of the design with post-layout timing (if desired). 14. Tape out after LVS and DRC verification. 1 Chapter 1 Physical Synthesis Traditionally synthesis methods are based on using the wire-load models. The basic nature of the wire-load models is such that they are fanout based. In other words, the delay computation of cells is performed based on the number of fanouts a cell drives.

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